1. Field of the Invention
The present invention relates to a bidirectional thyristor and, more particularly, to a bidirectional thyristor structure with single MOS gate controlled turn-off capability.
2. Description of the Related Art
Power semiconductor structures that combine bipolar conducting mechanisms with a MOS control are well known. The insulated gate bipolar transistor (IGBT) is an example of such a device, in which the base current of a bipolar structure is controlled via an integrated MOSFET. The IGBT is simple to control like a power MOSFET, but advantageously has a lower on-state voltage drop compared to power MOSFET for voltages greater than 500 volts. The on-state voltage drop of the IGBT is increased when IGBT is designed for higher blocking voltages (&gt;1000 V).
For higher voltages, a thyristor structure has been developed which advantageously has a lower on-state voltage drop compared to IGBT and in which a cathode short circuit is switched via a MOS gate. Such a structure, known as a MOS controlled thyristor or MCT, and described in an article by V. A. K. Temple, IEEE International Electron Device Meeting (IEDM) Technical Digest, San Francisco (December 1984), pp. 282-85, is turned on and off by a single MOS gate. While the MCT has an asymmetric structure and can conduct current in only one direction, bidirectional thyristor structures with MOS turn-off capability have also been developed--see, e.g., U.S. Pat. Nos. 4,816,892 and 5,040,042. These bidirectional thyristors are useful in ac switching applications.
In conventional MCTs and bidirectional thyristors, a lightly doped N.sup.- base region (the base region of the bottom PNP transistor) is used to support voltage in the blocking condition. For fast turn-off characteristics, the P base of the NPN transistor is desirably connected to ground potential and the N base of the PNP transistor is desirably connected to the high anode potential. However, connecting the N base to the high anode potential can only be achieved by using anode shorts, which destroys the reverse blocking capability of the device, or by using MOS gates on the back-side of the device, such as in U.S. Pat. Nos. 4,816,892 and 5,040,042, which makes device fabrication difficult.
U.S. Pat. No. 4,857,983 to Baliga et al. describes a device (FIG. 1) which, by using an N.sup.+ diffusion 20 on the backside of the wafer, achieves reverse conduction characteristics without the above-noted disadvantages. In FIG. 1, the device is turned-on in the forward direction (anode positive with respect to cathode) by applying a sufficiently positive potential to gate 2 to create an n-channel in the P.sup.- base 14, thus electrically coupling N.sup.+ region 7 and N.sup.+ region 8, which in turn is directly connected to cathode electrode 6. This couples the four layer structure formed by P layer 10, N.sup.- layer 12, P.sup.- region 14 and N.sup.+ region 7 to the cathode through the series n-channel MOSFET and the structure then assumes a regenerative conducting state, providing an active base drive to the inherent PNP bipolar transistor formed of P layer 10, N.sup.- layer 12 and P.sup.- 0 region 14. When the gate voltage is reduced sufficiently or made zero, N.sup.+ region 7 is decoupled from N.sup.+ region 8 and from the cathode, and conduction ceases.
As is apparent from the prior art FIG. 1 device, the boundary between N.sup.- layer 12 and P.sup.- region 14, and the boundary between N.sup.+ layer 12 and P.sup.+ region 16, form the forward blocking junctions of the device, and most of the blocking voltage is supported in the N.sup.- layer, the base region of the bottom PNP transistor. An inherent parasitic thyristor structure exists in the forward direction, formed by P layer 10, N.sup.- layer 12, P.sup.- region 14 and N.sup.+ region 8.
In the reverse direction (anode 4 negative with respect to cathode 6) and with a sufficiently negative potential applied to the gate structure 2 to keep all MOS gates at zero potential, conduction occurs through the four layer structure formed by P.sup.+ region 16, N.sup.- layer 12, P layer 10 and backside N.sup.+ region 20. This four layer structure provides regenerative conduction in the reverse direction. In response to the application of a sufficiently positive potential to gate structure 2, regenerative conduction of the four layer structure ceases because of the resulting n-channels created in P region 16, shorting N.sup.- layer 12 to N.sup.+ regions 22 and to cathode electrode 6 connected thereto. This short of the PN junction between P.sup.+ region 16 and N.sup.- layer 12 reduces the injection from this junction and interrupts regenerative conduction. The boundary between N.sup.31 layer 12 and P layer 10 forms the reverse blocking junction of the device, and most of the blocking voltage is supported in the N.sup.- layer, the base region of the upper PNP transistor.
Disadvantageously, in the device of FIG. 1, the N.sup.- base (N.sup.- layer 12) of the wide-base PNP transistor is not connected to the high anode potential when the device is turned-off from the forward conducting state, thus degrading the forward turn-off characteristics of the device. Also, as mentioned above, the device has an inherent parasitic thyristor which limits the MOS gate control capability of the device in the forward conducting state.
It is thus desirable to provide a single MOS gate controlled bidirectional thyristor without a parasitic thyristor and with improved turn-off characteristics.